Dipl.-Ing. Markus Winter
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Postal |
Technische
Universität Dresden |
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Barkhausenbau (BAR),
Room II/7e (second floor) |
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Phone: |
+49 351 463 41 048 |
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Fax: |
+49 351 463 41 099 |
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e-mail: |
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Scientific Interests
- System-on-Chip design and design automation
- Network-on-Chip design, architecture and design automation/generation
- Network-on-Chip management and QoS realization
Education, Vitae
Dec. 2005 Diplom-Ingenieur (equivalent to M.Sc.) in Information System Technology (Informationssystemtechnik) at TU DresdenSep. 2004 - Feb. 2005 Internship at Texas Instruments Germany in Freising
Dec. 2003 - June 2004 Student Assistant at Vodfone Chair Mobile Communications Systems, TU Dresden
Oct. 2002 - Feb. 2003 Tutor at Faculty for Mathematics and Science, TU Dresden
July 1999 Abitur M.-v.-Ardenne-Gymnasium Riesa
Projects
- Tommy/Atlas Multi-Processor System-on-Chip developed at Vodafone chair
- TOMAHAWK Multi-Processor System-on-Chip developed at Vodafone chair
Teaching Courses
- Winter semester 2008: Praktikum Mikrorechentechnik
- Summer semester 2008: Übung Einführung in die Nachrichtentechnik (Introduction to communications)
- Winter semester 2007: Praktikum Mikrorechentechnik
- Summer semester 2007: Übung Einführung in die Nachrichtentechnik (Introduction to communications)
- Winter semester 2006: Praktikum Mikrorechentechnik
- Summer semester 2006: Übung Einführung in die Nachrichtentechnik (Introduction to communications)
- Winter semester 2007: Nachrichtentechnik Seminar: MRAM, DRAM, SRAM, Flash,... - A Survey on Memory Types
- Summer semester 2007: Nachrichtentechnik Seminar: PCI and PCI Express Architecture
Student projects
Open Topics
Currently there are no open student projects. If you are still eager about NoC design and research, please contact me via E-mail or directly at the ChairRunning and Finished Student Projects
- Steffen Prusseit: Student Project, Since March 2010
Development and Analysis of Routing Algorithms in clustered and hierarchical Networks-on-Chip
- Friedrich Pauls: Student Project, Since June 2009
Development and Analysis of Slotted Guaranteed Service Channels in Network-on-Chip
- Christoph Gulich: Diploma Thesis, May 2009 - February 2010
Development and Analysis of a Central Unit for Allocation of Virtual Channels in Networks-on-Chip
- Christoph Gulich: Student Project, April 2008 - March 2009
Development and Implementation of a USB interface on an FPGA for the Tomahawk project
- Eric Wünsche: Student Project, Oct. 2008- June 2009
Development and Implementation of an Ethernet interface on an FPGA for the Tomahawk project
- Eric Wünsche: Student Assistant and Student Project, Nov. 2007 - August 2008
Development and Implementation of of I/O and hardware modules (e.g. SDRAM) on an FPGA for the Tomahawk project
- Lei Zhao: Student Assistant, May 2008 - Oct. 2008
Development and Analysis of a Routing Mechanism for Network-on-Chips with arbitrary and irregular topologies
- Jonas Eymann: Student Project, Feb. 2008 - Nov. 2008
Development and Analysis of Routers with Guaranteed Traffic in Networks-on-Chip
- Oliver Richter: Student Project, Dec. 2007 - Aug. 2008
Development and Analysis of Cache Coherence Protocols in Network-on-Chip based System-on-Chips
- Thilo Vörtler: Diploma Thesis, Oct. 2007 - June 2008
Development and Analysis of Different Routing Mechanisms and Architectures in Network-on-Chips
- Luis Francisco Martin Gil: Student assistant, May 2007 - Sep. 2007
Development of a Network-on-Chip generator as hardware design automation tool and a simulation model for Networks-on-Chip
- Patrick Grosa: Student assistant, Sep.2006 - Oct. 2006
Implementation of a Network-on-Chip architecture in Verilog HDL
Supervised Student Seminars
- Qingqing Xia: June 3, 2008
A Survey of Design Techniques for System-Level Dynamic Power Management
- Le Ahn Quang: Nov. 29, 2007
Verification Techniques for Embedded Processor Design
- Thomas Klotz: June 5, 2007
From Algorithm to RTL with SystemC in Hardware Design
Publications
- E. Matus, T.Limberg, M. Winter, M. Bimberg, R. Klemm, M.B.S. Tavares, H. Ahlendorf and G. Fettweis
Multi-Processor SDR Platform with HW Supported Dynamic Scheduling,
In Proceedings of the 12th Symposium on Low-Power and High-Speed Chips (COOLChips'09), Yokohama, Japan, April 15 - 17, 2009.
- T. Limberg, M. Winter, M. Bimberg, R. Klemm, M.B.S. Tavares, H. Ahlendorf, E. Matus, G. Fettweis,
H. Eisenreich, G. Ellguth and J.-U. Schlüssler
A Heterogeneous MPSoC with Hardware Supported Dynamic Task Scheduling for Software Defined Radio,
DAC/ISSCC Student Design Contest, San Francisco, CA, USA, February 8 - 12 and July 26 - 31, 2009.
2009 DAC/ISSCC Student Design Contest Winner.
- T. Limberg, M. Winter, M. Bimberg, R. Klemm, E. Matus, M.B.S. Tavares, G. Fettweis, H. Ahlendorf, P. Robelly
A Fully Programmable 40 GOPS SDR Single Chip Baseband for LTE/WiMAX Terminals,
34th European Solid-State Circuits Conference (ESSCIRC'08), Edinburgh, Great Britain, September 15 - 19, 2008.
2009 VDE/VDI-GMM Prize Winner.
- M. Winter and G. Fettweis,
A Network-on-Chip Channel Allocator for Run-Time Task Scheduling in Multi-Processor System-on-Chips,
Proceedings of 11th EUROMICRO Conference on Digital System Design (DSD), Parma, Italy, September 3 - 5, 2008, pp. 133-140.
- M. Winter and G. Fettweis,
Interconnection Generation For System-on-Chip Design,
Proceedings of International Symposium on System-on-Chip 2006, Tampere, Finland, November 13 - 16, 2006, pp. 91-94.
- M. Winter and G. Fettweis,
Interconnection Generation For System-on-Chip Design,
Presented at Kleinheubacher Tagung, Miltenberg, Germany, September 25 - 29, 2006.
- M. Winter and G. Fettweis,
Interconnection Architecture For System-on-Chip Design Providing Little Overhead, Low Latency and High Throughput,
9th EUROMICRO Conference on Digital System Design (DSD), Cavtat/Dubrovnik, Croatia, August 28th - September 1st 2006.